A source/drain region and a gate electrode of a MOS transistor are electrically insulated from each other by a gate insulating film present between the source/drain region and the gate electrode. Since the lower edge of the gate electrode is formed into a sharp shape, electric fields are concentrated on the lower edge of the gate electrode. The enhancement of the electric fields causes dielectric failure in insulating between the source/drain region and the gate electrode.
The gate insulating film adjacent to the lower edge of the gate electrode sustains process damage owing to etching which is performed when the gate electrode is formed or ion implantation which is performed when the source/drain region is formed. The deterioration in the insulation resistance is caused by the process damage. The deterioration in the insulation resistance results in the dielectric failure to becomes more critical.
The foregoing states also applies to the lower edge of a floating gate electrode of a flash memory cell as well as the lower edge of the gate electrode of the MOS transistor. That is, the foregoing fact usually applies to an insulating gate transistor of a type incorporating a gate electrode having a sharp edge and disposed opposite to a semiconductor substrate through a gate insulating film.
As a conventional technique for overcoming the foregoing problem of the dielectric failure, a post-oxidation process is known. As shown in FIG. 10A, the foregoing process has the steps of sequentially forming a silicon oxide film 92 and a low-resistance polycrystalline silicon film 93 containing dopant on a silicon substrate 91. Then, the polycrystalline silicon film 93 is formed into a predetermined pattern, and then, as shown in FIG. 10B, thermal oxidation is performed in an oxygen (O2) atmosphere so that a post oxide film 94 is formed. Since the post oxide film 94 is formed, the sharp lower edge of the polycrystalline silicon film 93 can be rounded. Thus, the electric field at the lower edge is moderated.
Birds beak oxidation occurring when the thermal oxidation is performed enlarges the distance between the lower edge of the polycrystalline silicon film 93 and the silicon substrate 91. Thus, the electric field at the lower edge can be weakened. When the distance between the substrate and the lower edge is elongated, the distribution of the electric fields is not changed. The overall intensity of the electric field is, however, weakened, causing the electric field at the lower edge to be moderated.
The silicon oxide film 92 present adjacent to the edge of the polycrystalline silicon film 93 and which has sustained the process damage is permitted to restore its process damage owing to the post oxidation which is additional oxidation. Thus, the film quality of the silicon oxide film 92 can be improved so that the insulation resistance of the silicon oxide film 92 is improved.
The foregoing post oxidation process attains a similar effect when an overetching structure as shown in FIGS. 11A and 11B is subjected to the process. FIGS. 11A and 11B show a structure that also the silicon oxide film 92 which is present below the polycrystalline silicon film 93 which must be removed when the polycrystalline silicon film 93 is patterned. Moreover, the surface of the silicon substrate 91 below the silicon oxide film 92 has been removed.
As described above, employment of the post oxidation process enables a dielectric failure caused from enhancement of electric fields at the lower edge of the polycrystalline silicon film 93 to be avoided.
As a conventional method for converting a silicon nitride film into silicon oxide film, a thermal oxidation method using steam or oxygen (O2) gas as an oxidizer, or a plasma oxidation method using oxygen gas or ozone gas as a source and arranged to be performed in a plasma atmosphere is known.
The foregoing method has the following problems. When the thermal oxidation method is employed, a great thermal budget is required to be performed at high temperatures for a long time. When the surface of a silicon nitride film formed by an LPCVD method is formed into silicon oxide film having a thickness of 5 nm, great thermal budget must be performed at 950° C. for about one hour even when a steam oxidation method exhibiting a high oxidation rate is employed.
When the thermal budget is too great, dopant in the silicon substrate encounters thermal diffusion. Thus, the concentration profile of the dopant is undesirably changed. Therefore, the thermal oxidation method cannot easily be applied to a process for treating small devices.
When the plasma oxidation method is employed, the body which must be processed is exposed to plasma. Therefore, for example, the gate insulating film sustains plasma damage. The foregoing plasma damage causes deterioration in the reliability of the insulating film and undesirably change in the characteristics of the device.
The conventional techniques and their problems will now be described.
FIG. 12A to 12D are cross sectional views showing steps of a method of forming a small-size MOS transistor superior to the lithography performance. As shown in FIG. 12A, a gate insulating film 102, a polycrystalline film 103 which is formed into a gate electrode and a silicon nitride film 104 which serves as a mask (a SiN pattern) for use when the polycrystalline silicon film 103 is etched are sequentially formed on a silicon substrate 101 having a surface into which dopant has been introduced by an ion implantation method.
Then, as shown in FIG. 12B, resist is applied to the overall surface to transfer a gate pattern having a minimum width which can be realized by the lithography technique to the resist. Thus, a resist pattern 107 (a portion indicated with a dashed line) is formed. Then, an oxidation process which is process under a reduced pressure and using radical oxygen is performed to reduce the width of the resist pattern 107. The drawing shows the resist pattern 105 having the reduced width with a solid line.
Then, as shown in FIG. 12C, the resist pattern 105 is used as a mask to etch the silicon nitride film 104 by RIE (Reactive Ion Etching) method so that a SiN pattern is formed. Then, the resist pattern 105 is removed.
Then, as shown in FIG. 12D, the residual silicon nitride film (the SiN pattern) 104 is used as a mask to etch the polycrystalline silicon film 103 by the RIE to form a gate electrode having a small size superior to the performance of the lithography.
Finally, as shown in FIG. 12D, the gate electrode (the polycrystalline silicon film) 103 is used as a mask to implant dopant ions into the surface of the substrate. Then annealing is performed to activate the dopant so that a source/drain region 106 is formed. Thus, a MOS transistor is manufactured.
The foregoing conventional method requires the film thickness of the resist which is applied in the step shown in FIG. 12B to be about 500 nm in a usual case. Therefore, when the gate electrode 103 having a width of, for example, 50 nm is formed, the aspect ratio of the resist pattern 105 is undesirably raised to 10.
Therefore, the shape of the resist pattern 105 easily disperses. As a result, there arises a problem in that the shape of the gate electrode 103 dispersed. Another problem arises in that the resist pattern 105 falls.
As an alternative to reduction in the width of the resist pattern 105, a technique is known with which the width of the SiN pattern film 104 is reduced. That is, the conventional method has the arrangement that the SiN pattern 104 having the minimum width which can be realized by the lithography technique is formed, and then the oxidation process is performed to reduce the SiN pattern 104.
However, the width of the SiN pattern 104 cannot easily be reduced to a required width. When the steam oxidation method exhibiting a high oxidation rate is employed, thermal budget at 950° C. for one or more hours must be performed to reduce the width of the SiN pattern 104 by 10 nm. When the foregoing high-temperature and long oxidation process is performed, there arises a problem in that the concentration profile of the dopant in the silicon substrate 101 is considerably changed.